1. Field of the Invention
This invention relates generally to processors and, more specifically, to a processor architecture scheme and method which allows for the encoding of multiple addressing modes through virtual register addresses to maximize the number of directly addressable registers in the processor architecture scheme.
2. Description of the Prior Art
Generally speaking, a processor is an entity where a central processing unit (CPU) is present and is used to fetch and execute stored instructions or microcode. Some examples of processors are microcontrollers, microprocessors, and digital signal processors. Each type of processor operates on data which is also commonly referred to as operands. This data is generally stored in registers or memory space.
An instruction directs the CPU of a processor to execute a certain operation as well as to identify one or more operand(s) for the operation. Processors offer various means for addressing the data for an operation. These means are commonly referred to as addressing modes. The addressing modes are typically used for arithmetic and logical operations and data move operations and may apply to a source operand, a destination operand, or both.
The problem with current processor architecture schemes is that adding or changing addressing modes is extremely difficult. Without major changes to the instruction set organization, such changes and additions to the addressing modes are not possible. However, changes to the instruction set structure is not desirable since many tools such as assemblers and compilers will also require dramatic changes.
Another problem with the traditional method of encoding addressing modes in an instruction is that the number of directly o addressable xe2x80x9cregistersxe2x80x9d diminish significantly. For example, if 8-bits are available in an instruction word to specify a register operand, it would be possible to address 256 registers directly. However, in order to incorporate other addressing modes, and one of the 8-bits is taken away for this purpose, only 128 registers can now be directly addressed.
In existing processor architecture schemes, where alternate addressing modes are available, encoding is implemented through xe2x80x9ccontrol registersxe2x80x9d in order to maximize the number of directly addressable registers. However, this creates yet another problem since xe2x80x9cselectionxe2x80x9d of indirect addressing modes is static (until reconfigured) and not dynamic from instruction to instruction.
Therefore, a need existed to provide an improved microcontroller architecture scheme. The improved microcontroller architecture scheme must allow the user to add and change addressing modes. The improved microcontroller architecture scheme must further allow the user to change addressing modes dynamically on an instruction by instruction basis.
In accordance with one embodiment of the present invention, it is an object of the present invention to provide an improved microcontroller architecture scheme.
It is another object of the present invention to provide an improved microcontroller architecture scheme that allows the user to add and change addressing modes.
It is yet another object of the present invention to provide an improved microcontroller architecture scheme that allows the user to add and change addressing modes while maximizing the number of directly addressable registers.
It is still a further object of the present invention to provide the aforementioned improvements to the microcontroller architecture scheme while maintaining the ability to choose addressing modes dynamically on an instruction by instruction basis.
In accordance with one embodiment of the present invention, a processor architecture scheme which allows for encoding of multiple addressing modes through use of virtual register addresses in order to maximize number of directly addressable registers in the processor architecture scheme is disclosed. The processor architecture scheme comprises the steps of: providing an instruction set for the processor to execute; dedicating a first section of each instruction of the instruction set to identify where each instruction is to be executed; establishing an indirect addressing pointer in memory; and establishing a dedicated set of the virtual register addresses in the memory equal to a number of indirect addressing modes associated with the indirect addressing pointer wherein each of the virtual register addresses dictate an indirect addressing mode to be used with the indirect addressing pointer when accessed thereby allowing flexibility of selecting addressing modes dynamically on an instruction by instruction basis.
In accordance with another embodiment of the present invention, a processor architecture scheme which allows for encoding of multiple addressing modes through use of virtual register addresses in order to maximize number of directly addressable registers in the processor architecture scheme is disclosed. The processor architecture scheme uses a central processing unit for executing the instruction. A memory unit is coupled to the CPU for storing data. A pointer register is established in the memory for storing an address location where the instruction is to access when an address associated with the pointer register is accessed. Dedicated virtual register address locations in the memory are established. The dedicated virtual register address locations associated with the pointer register dictates indirect addressing modes to be used with the pointer register when one of the dedicated address locations is accessed thereby allowing flexibility of selecting addressing modes dynamically on an instruction by instruction basis.